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19-2265; Rev 0; 12/01
MAX3670 Evaluation Kit
General Description
The MAX3670 evaluation kit (EV kit) is an assembled, surface-mount demonstration board that provides easy evaluation of the MAX3670 155MHz to 670MHz reference clock generator. The EV kit comes with external components and a 622.08MHz voltage-controlled crystal oscillator (VCXO). o Fully Assembled and Tested o 5.0V Operation
Features
Evaluates: MAX3670
Ordering Information Component Suppliers
SUPPLIER AVX Coilcraft Murata Vectron PHONE 843-448-9411 408-224-8566 770-436-1300 1-88-VECTRON-1 FAX 843-448-1943 408-224-6304 770-436-3030 1-888-PAX-VECTRON PART MAX3670EVKIT TEMP RANGE -40C to +85C IC PACKAGE 32 QFN-EP*
*Exposed pad
Electrical Component List
DESIGNATION C1, C4-C9, C12, C15, C16, C20, C22, C31-C35 C1A, C1B C2, C3, C3A, C10, C11, C14, C19, C21, C23-C27, C29, C30 C3B C13 C17 J1-J8, J11 J9, J10, J12, J15, J16 J13, J14 JU1-JU5, JU7-JU10 JU1-JU13 JU6, JU11, JU12, JU13 L1, L3, L4 L2 QTY DESCRIPTION 0.1F 10% ceramic capacitors (0402) 0.015F 10% ceramic capacitors (0805) DESIGNATION R1, R11, R12, R13, R18-R21, R23, R24, R26, R27, R29, R31 R1A, R1B R2 R3, R4, R6, R8, R10, R16, R17 0 Open R5, R7, R9, R14, R15, R22, R28, R30, R32 U1 Y1 None None 0 2 9 13 4 0 1 Open Test points 1 x 3-pin headers Shunts 1 x 2-pin headers Open 56nH inductor None 9 1 1 1 1 1 0 resistors (0402) MAX3670EGJ 32 QFN-EP 622.08MHz voltage-controlled SAW oscillator Vectron VS500A622 MAX3670 EV kit circuit board MAX3670 EV kit data sheet MAX3670 data sheet QTY DESCRIPTION
17
0
Open
2
2 1 7
200k 1% resistors (0402) 100 1% resistor (0402) 332 1% resistors (0402)
1 1 1 9
6800pF 10% ceramic capacitor (0805) 1F 10% ceramic capacitor (0805) 10F 10% tantalum capacitor SMA connectors (edge-mount)
________________________________________________________________ Maxim Integrated Products
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For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
MAX3670 Evaluation Kit Evaluates: MAX3670
Quick Start
1) Install shunts JU1, JU4, JU5, JU7, and JU10 between pins 1 and 2. 2) Install shunts JU11, JU12, and JU13. 3) Open shunts JU3 and JU6. 4) Install shunts JU2, JU8, and JU9 between pins 2 and 3. 5) Connect a 5V power supply to VCCA. 6) Connect ground to GND. 7) Apply a 1VP-P differential clock input at 622.08MHz to REFCLK+ and REFCLK-. 8) Monitor MOUT+ and MOUT- with a 50 system. A 622.08MHz clock signal appears on the oscilloscope.
Adjustment and Control Descriptions*
COMPONENT JU1 NAME GSEL1 FUNCTION Sets the phase-detector gain (KPD) and the frequency divider ratio (N2). Shunting between pins 1 and 2 sets to GND. Shunting between pins 2 and 3 sets to VCC (see Table 1). Sets the phase-detector gain (KPD) and the frequency divider ratio (N2). Shunting between pins 1 and 2 sets to GND. Shunting between pins 2 and 3 sets to VCC (see Table 1). Sets the phase-detector gain (KPD) and the frequency divider ratio (N2). Shunting between pins 1 and 2 sets to GND. Shunting between pins 2 and 3 sets to VCC (see Table 1). Sets the predivider ratio for the reference input clock. Shunting between pins 1 and 2 sets to GND. Shunting between pins 2 and 3 sets to VCC (see Table 2). Sets the predivider ratio for the VCO input clock. Shunting between pins 1 and 2 sets to GND. Shunting between pins 2 and 3 sets to VCC (see Table 3). Open when VCO is activated. Closed when VCO is disabled. Sets the internal compensation of the op amp. Shunting between pins 1 and 2 sets the compensation to GND. Shunting between pins 2 and 3 sets the compensation to VCC. Sets the output clock divider. Shunting between pins 1 and 2 sets to GND. Shunting between pins 2 and 3 sets to VCC (see Table 4). Sets the output clock divider. Shunting between pins 1 and 2 sets to GND. Shunting between pins 2 and 3 sets to VCC (see Table 4). Sets the polarity of the op amp. Shunting between pins 1 and 2 sets the polarity to GND. Shunting between pins 2 and 3 sets the polarity to VCC.
JU2
GSEL2
JU3
GSEL3
JU4 JU5 JU6 JU7
RSEL VSEL -- COMP
JU8 JU9 JU10
PSEL2 PSEL1 POLAR
*See Quick Start first.
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MAX3670 Evaluation Kit
Adjustment and Control Descriptions (continued)
COMPONENT JU11 JU12 JU13 NAME -- -- -- Ensure that shunt is installed. Ensure that shunt is installed. Ensure that shunt is installed. FUNCTION
Evaluates: MAX3670
Table 1. Gain Logic Pin Setup
INPUT PIN GSEL1 VCC OPEN GND VCC OPEN GND VCC OPEN GND VCC OPEN VCC OPEN GND VCC OPEN GND VCC OPEN GND VCC OPEN INPUT PIN GSEL2 VCC VCC VCC OPEN OPEN OPEN GND GND GND VCC VCC VCC VCC VCC OPEN OPEN OPEN GND GND GND OPEN OPEN INPUT PIN GSEL3 VCC VCC VCC VCC VCC VCC VCC VCC VCC GND GND OPEN OPEN OPEN OPEN OPEN OPEN OPEN OPEN OPEN GND GND KPD (A/UI) 20 20 20 20 20 20 20 20 20 20 20 5 5 5 5 5 5 5 5 5 5 5 DIVIDER RATIO N 1 2 4 8 16 32 64 128 256 512 1024 1 2 4 8 16 32 64 128 256 512 1024
Table 2. Reference Clock Divider
INPUT PIN RSEL VCC OPEN GND REFERENCE CLOCK INPUT FREQ (MHz) 77.76 155.52 622.08 DIVIDER RATIO (N3) 1 2 8 PREDIVIDER OUTPUT FREQ (MHz) 77.76 77.76 77.76
Table 3. VCO Clock Divider
INPUT PIN VSEL VCC OPEN GND VCO CLOCK INPUT FREQ (MHz) 77.76 155.52 622.08 DIVIDER RATIO (N1) 1 2 8 PREDIVIDER OUTPUT FREQ (MHz) 77.76 77.76 77.76
Table 4. Optional Clock Output Divider
INPUT PIN PSEL1 VCC GND VCC GND INPUT PIN PSEL2 VCC VCC GND GND VCO TO POUT DIVIDE RATIO 1 2 4 8
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Evaluates: MAX3670
VCCA R19 OPEN R1B 200k R24 OPEN C3B 6800pF R23 OPEN VCCA R3 332 J11 R28 0 R31 OPEN VCCA R27 OPEN J10 J7 R17 332 C9 0.1F R15 0 Y1 24 23 22 J6 21 VTT R7 0 C7 0.1F J5 J8 20 VCCD 19 R5 0 C6 0.1F J4 C5 0.1F R30 0 VTT R8 332 R10 332 R12 OPEN R16 332 VCCD R9 0 C8 0.1F C12 0.1F R14 0 VVCO R11 OPEN VEE OD VC SAW-OSC 3 2 1 JU6 JU7 JU8 R29 OPEN VCCA 32 VCCA PSEL2 OPAMP+ OPAMPC2+ VCOIN+ VCOINVCCO2 U1 MOUT+ C2COMP PSEL1 1 2 3 VCCD 4 THADJ 5 CTH MOUTVCCO POUT+ 18 VTT POUT- 17 VCCD VSEL VTT R4 332 J12 VVCO TP2 VCCD VCCD JU4 R2 100 R21 OPEN C15 0.1F C4 0.1F R1 OPEN L2 56nH J13 VCCA JU5 C3 OPEN R6 332 GSEL1 PO1 VC 31 30 29 28 27 26 25 R13 OPEN JU9 JU10 VCCD VCCD VCCA R32 0 C3A OPEN R1A 200k R26 OPEN C1A 0.015F C1B 0.015F VCCA R20 OPEN R22 0 VCCA
VCCD
LOL
GND
RSEL
REFCLK+
JU2 VCCD 9 VCCD 10 11 12 13 14 15 16
REFCLK-
Figure 1. MAX3670 EV Kit Schematic
4 OUT 5 OUT 6 VCC
MAX3670 Evaluation Kit
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MAX3670
6 7 GSEL2 8 GSEL3 J3 L1 OPEN VVCO C16 0.1F C14 OPEN C19 OPEN J14 GND L3 OPEN J15 VTT C17 10F C20 0.1F C21 OPEN C22 0.1F C1 0.1F JU12 VTT JU13 JU11 VCCA J1 J2 J16 VCCD L4 OPEN C23 OPEN C29 OPEN C24 OPEN C30 OPEN C25 OPEN C31 0.1F C26 OPEN C32 0.1F C27 OPEN C33 0.1F VCCD C10 OPEN C34 C35 0.1F 0.1F
J9
C11 OPEN
R18 OPEN
C2 OPEN
VCCD
TP1
VCCD
C13 TP3 1F
JU1
VCCD
VCCD
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JU3
MAX3670 Evaluation Kit Evaluates: MAX3670
1.0"
1.0"
Figure 2. MAX3670 EV Kit Component Placement Guide-- Component Side
Figure 3. MAX3670 EV Kit Component Placement Guide-- Solder Side
1.0"
1.0"
Figure 4. MAX3670 EV Kit PC Board Layout--Component Side
Figure 5. MAX3670 EV Kit PC Board Layout--Solder Side
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MAX3670 Evaluation Kit Evaluates: MAX3670
1.0"
1.0"
Figure 6. MAX3670 EV Kit PC Board Layout--Ground Plane
Figure 7. MAX3670 EV Kit PC Board Layout--Power Plane
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
6 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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